Packaging Substrates

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Organic Packaging Chip Substrates

Substrate technology is the foundation of semiconductor packaging and one of the most critical factors in chip and system performance. As semiconductor and packaging technologies rapidly evolve, organic substrate solutions must follow. To stay ahead of the game, suppliers of advanced chip substrates require not only technological capabilities but even more so a genuine understanding of the specific needs that drive the chip-packaging industry.

DYCONEX is an exceptional supplier of advanced organic packaging substrates from prototypes up to mid-volume production. With out-of-the box thinking, DYCONEX provides added value through creative interconnect solutions and exceptional engineering expertise.

Our substrates are designed for wide variety of packaging solutions including:

  • SiP (system in package) and MCM (multichip module) substrates
  • RFIC (radio frequency IC) chip substrates in LCP (liquid crystal polymer)
  • Singulated and matrix BGA (ball grid array) and SDBGA (stacked die BGA) substrates
  • CSP (chip scale packaging) substrates


Technology Highlights

  • Ultra-thin materials for light-weight build-ups
  • High Tg, low CTE and high dielectric strength
  • Stacked anylayer vias and via-in-pad
  • High density pitch design (175 µm)
  • High precision cavities for die placement
  • Impedance controlled ultra-fine line technology
  • Anylayer or HDI technology
  • RFIC LCP substrates
  • Near hermetic packaging - SAW (surface acoustic wave) and BAW (bulk acoustic wave) filters

 

General capabilities for packaging boards:

Description

Standard Capabilites

Lines/spaces

35/40 µm

Microvias/pads diameter (laser)

75/200 µm

Through vias/pads diameter (mechanical)

125/250 µm

Thinnest starting material

40 µm

Thinnest dielectric thickness

40 µm

Conductor width tolerance

+/- 20%

Artwork to soldermask tolerance

+/- 25 µm

Layer count

20+

Description

Leading-Edge capabilities

Lines/spaces

25/35 µm

Microvias/pads diameter (laser)

50/100 µm

Through vias/pads diameter (mechanical)

100/180 µm

Thinnest starting material

30 µm

Thinnest dielectric thickness

30 µm

Conductor width tolerance

+/- 15%

Artwork to soldermask tolerance

+/- 15 µm

Layer count

up to 24


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