DYCONEX AG recently installed its fourth IST (interconnect stress test) testing machine and in doing so further upgraded its Center of Competence for product reliability.
DYCONEX AG has successfully completed certification according to EN 9100:2009 – the international quality management standard for the aviation and aerospace industry – and has now been added to the OASIS (Online Aerospace Supplier Information System) database.
Microelectronics & Packaging
September 10 - 13, 2017
University of Technology, Warsaw, Poland
September 13, 2017
Convention Center, Santa Clara, CA, USA
October 10 - 11, 2017
Raleigh, NC, USA
As PCB design complexity and density continue to increase, front-end data preparation efforts must be evermore exact and provide production artwork that is tailored to meet specific customer requirements. A challenging example is provided by the case where the customer has defined specific line width targets and provided tolerance ranges that, as a percentage of nominal target line width, must be met everywhere on the circuit. Due to the dependency of etch rate upon design spacing, it follows that some circuit elements may need to be individually compensated according to the localized spacing conditions inherent to the design. With especially complex designs this mostly manual effort can be very tedious and time consuming, often overreaching the available time or human resources allocated to complete the task.
With the objective of becoming faster, more accurate, and more cost-effective in the data prep tasks as described, DYCONEX has implemented a new software application named TEC (True Etch Compensation) that will largely automate this process. Additional benefits may likewise be seen long-term in the form of higher process stability and higher production yields.
© 2017 Micro Systems Technologies, CH-6340 Baar, Switzerland
DYCONEX AG, CH-8303 Bassersdorf, Switzerland