As PCB design complexity and density continue to increase, front-end data preparation efforts must be evermore exact and provide production artwork that is tailored to meet specific customer requirements. A challenging example is provided by the case where the customer has defined specific line width targets and provided tolerance ranges that, as a percentage of nominal target line width, must be met everywhere on the circuit. Due to the dependency of etch rate upon design spacing, it follows that some circuit elements may need to be individually compensated according to the localized spacing conditions inherent to the design. With especially complex designs this mostly manual effort can be very tedious and time consuming, often overreaching the available time or human resources allocated to complete the task.
With the objective of becoming faster, more accurate, and more cost-effective in the data prep tasks as described, DYCONEX has implemented a new software application named TEC (True Etch Compensation) that will largely automate this process. Additional benefits may likewise be seen long-term in the form of higher process stability and higher production yields.
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DYCONEX AG, CH-8303 Bassersdorf, Switzerland